This invention relates generally to clock data recovery circuitry, and more particularly to wide range and dynamically reconfigurable clock data recovery circuitry that can be provided on or in association with programmable logic devices.
An increasingly important type of signaling between devices is signaling in which the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in “packets” of several successive serial data words preceded by a serial “header” that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver the clock signal is “recovered” from the data signal for use in properly processing the data in the data signal. For convenience herein this general type of signaling will be referred to generically as “clock data recovery” or “CDR” signaling.
CDR signaling is now being used in many different signaling protocols. These protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc.
Programmable logic devices (“PLDs”) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
CDR signaling is an area in which it would be highly desirable to have the ability to support a large number of communications standards. Since CDR signaling eliminates tight routing signal requirements, systems may be created with many different independent clock domains. These clock domains may support a variety of communications standards and protocols. For example, GIGE, XAUI, PIPE, SONET, and PCI-E are just a sample of the standards and protocols that may be supporting using CDR signaling. These standards and protocols may specify a wide range of data rates to support various applications. Accordingly, it would be desirable to provide a high performance, low power CDR architecture that is operable over a wide range of data rates. In addition, it would be further desirable to provide CDR architecture that is dynamically reconfigurable to support these various standards and protocols on-the-fly without disrupting other parts of the device.
The invention also includes methods of operating circuitry of the types summarized above.
Further features of the invention, its nature and various advantages, will become more apparent from the accompanying drawings and the following detailed description.